MODULE-2
1. Reduce the expression in SOP and POS form using K-map. F(A,B,C,D) = ∑m (1,5,6,12,13,14) + d(2,4)
2. Explain briefly 3 to 8 line decoders.
3. What is a multiplexer? The logic circuit and function table explain the working of 4 to 1 line multiplexer.
4. Draw 1) logic circuit of 4:1 MUX (2) logic diagram of 3-line to 8-line decoder (3) logic circuit of Full Adder and Full Subtractor with truth table. (4) logic circuit of 2x4 Decoder (5) logic circuit for 2-Bit Magnitude Comparator
5. Realize the expression Y(A, B, C, D) = Ʃ m(15, 7, 4, 6, 8, 9, 12, 14) using an 8:1 MUX.
6. Design (1) 1-Bit Full Adder using 3x8 Decoder. (2) full adder and realization full adder using 3X8 Decoder and 2 OR gates.
7. Solve the following Boolean functions by using K-Map. Implement the simplified function by using logic gates F = (w,x,y,z) = Σ (0,1,4,5,6,8,9,10,12,13,14)
8. With a neat block diagram explain the function of the encoder. Explain priority encoder?
9. Implement the following Boolean functions with a multiplexer and Decoder. F(w, x, y, z) = Σ (2, 3, 5, 6, 11, 14, 15)
10. Design a combinational logic circuit whose output is high only when the majority of inputs (A, B, C, D) are low.
11. Explain working of Half Adder circuit with diagram.
12. How to generate 8x1 MUX using 4x1 MUX.
13. Implement the following function using 8X1 MUX F (A, B, C, D) = Σ m (0, 1, 3, 4, 8, 9, 15)
14. A combinational circuit is defined by the function F1 (A, B, C,) = Σ m (4, 5, 7) F2 (A, B, C,) = Σ m (3, 5, 7) Implement the circuit with a PLA having 3 inputs, 3 product term & 2 outputs.
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